PhD Computer Science
Performance Engineering at Yahoo
Working at Yahoo part of the Performance Engineering Group.
CPU Performance Modeling
Processor Architect
Microarchitecture Modeling
Work experience
Yahoo!
2012 - present
· Analyze CPU performance monitoring hardware and software interaction
· Intel Xeon Phi Coprocessor Benchmarking
· Intel Compiler and GCC test and benchmarks
· Hardware Certification (Intel and AMD CPU’s - Nvidia and AMD GPGPU’s)
· Linux RHEL and FreeBSD Certification- development and scripting the Certification
Process.
· Applications and Code optimization/ Compilers design.
· CPU/GPU Benchmarking
· Development and Deployment of the 10GbE Benchmark Tool.
· Secure Sockets Layer acceleration: Development of SSL-Accelerators, GPU's and Intel Xeon Phi Coprocessor implementation for Crypto-libraries (RSA-2k)
· Hadoop framework and clusters manipulation
. OpenStack Benchmarking Tools and Cloud Computing Projects management.
Research
2008 - 2012
02-06/2012 Post-doctoral position at Waterloo University, Canada.
Instrumentation framework (LLVM) Compilers and analysis tool.
06-12/2011 Post-doctoral fellowship in LIRMM Laboratory, Dali Group,
University of Perpignan-UPVD, France.
01-05/2011 Post-doctoral Internship, Thomas M. Siebel Center for Computer Science, University of Illinois-UIUC, Urbana-Champaign, IL - USA.
09-12/2010 Post-doctoral fellowship in LIRMM Laboratory, Dali Group,
University of Perpignan-UPVD, France.
Languages
C, C+, Java
Python, Perl, Bash
HTML/CSS
PHP
Delphi
Skills
Server, CPU, Disk and Network
Benchmarking and Profling
Intel and AMD CPUs
ARM Microarchitecture
Intel VTune Amplifier
Intel Compiler - ICC
Cilk Plus
Intel Xeon Phi
SSL Acceleration
Network Evaluation
2010 - present
2010 - present
Education
2007 – 2010 Ph.D in Computer Science (Computer Architecture),
University of Perpignan Via Domitia, UPVD- France, (With Highest Honors)
2004 – 2006 Master of Science, Computer Architecture
1998 – 2003 Bachelor - Computer Science, Software Engineering
Ph.D THESIS - 2010
Title of thesis: Tools for analysis and evaluation of processor performance.
Key words: UNISIM framework, Parallelism, CLM/TLM Simulation and Emulation, Compiler design, Performance analysis tools
Objective of thesis: Developing OoOSIM, a PowerPC Simulator. OoOSIM has a design methodology of simulated components to facilitate the duplication of units. The vectorization of the modules, is my contribution. My experiments show that without the application of vectorization, the simulation of a multi-core processor becomes very time consuming to load when the number of cores increases, even modestly show that vectorization can be simulated in reasonable CPU time with number of cores far beyond that offer products today.
MASTER THESIS - 2006
Title of thesis: Improving the performance of processors based on a distributed execution.
Key words: Superscalar processors, Trace/ Execution driven Simulation and Benchmarking (SPEC CPU, MiBench), Instruction Level Parallelism, Simplescalar.
Abstract: The CPU register file with its access ports and the mechanism of reference are the critical resources of processor’s data way. My master thesis evaluates the impact of the increase in the superscalar degree on the data flow handled by the processor.